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8-bit single-chip microcontrollers gms77c1000 GMS77C1001 users manual (ver. 1.1)
version 1.1 published by mcu application team 2001 hynix semiconductor all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and representatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way res ponsible for any violations of patents or other rights of the third party generated by the use of this manual.
gms77c1000/GMS77C1001 july. 2001 ver 1.1 contents of table overview . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . 2 pin assignment . . . . . . . . . . . . . . . . . . . 3 package diagram . . . . . . . . . . . . . . . . . 4 pin function . . . . . . . . . . . . . . . . . . . . . . 6 port structures . . . . . . . . . . . . . . . . . 7 electrical characteristics . . . . . . 9 absolute maximum ratings . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . 9 dc characteristics (1) . . . . . . . . . . . . . . . . . . 10 dc electrical characteristics (2) . . . . . . . . . . 11 ac electrical characteristics (1) . . . . . . . . . . 12 ac electrical characteristics (2) . . . . . . . . . . 13 typical characteristics . . . . . . . . . . . . . . . . . . 14 architecture . . . . . . . . . . . . . . . . . . . 17 cpu architecture . . . . . . . . . . . . . . . . . . . . . . 17 memory . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program memory . . . . . . . . . . . . . . . . . . . . . . 18 data memory . . . . . . . . . . . . . . . . . . . . . . . . . 18 special function registers . . . . . . . . . . . . . . 19 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . 23 port ra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 port rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 i/o interfacing . . . . . . . . . . . . . . . . . . . . . . . . . 23 i/o successive operations . . . . . . . . . . . . . . . 23 timer0 module and tmr0 register 25 timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 counter mode . . . . . . . . . . . . . . . . . . . . . . . . 26 using timer0 with an external clock . . . . . . . 27 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 configuration area . . . . . . . . . . . . . 29 oscillator circuits . . . . . . . . . . . . . 30 xt, hf or lf mode . . . . . . . . . . . . . . . . . . . . 30 rc oscillation mode . . . . . . . . . . . . . . . . . . . 30 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 power-on reset (por) . . . . . . . . . . . . . . . . . 33 internal reset timer (irt) . . . . . . . . . . . . . . . 35 watchdog timer (wdt) . . . . . . . . . . . 36 wdt period . . . . . . . . . . . . . . . . . . . . . . . . . . 36 wdt programming considerations . . . . . . . . 36 power-down mode (sleep) . . . . . . . . . . 37 sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 wake-up from sleep . . . . . . . . . . . . . . . . . . 38 minimizing current consumption . . . . . . . . . . 38 time-out sequence and power down status bits (to/pd) . . . . . . . . . . . . . 40 power fail detection processor 41
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 1 gms77c1000 / GMS77C1001 cmos single-chip 8-bit microcontroller 1. overview 1.1 description the gms77c1000 and GMS77C1001 are an advanced cmos 8-bit microcontroller with 0.5k/1k words(12-bit) of eprom. the hynix semiconductor gms77c1000 and GMS77C1001 are a powerful microcontroller which provides a high flexibility and cost effective solution to many small applications. the gms77c1000 and GMS77C1001 provide the follow- ing standard features: 0.5k/1k words of eprom, 25 bytes of ram, 8-bit timer/counter, power-on reset, on-chip oscillator and clock circuitry. in addition, the gms77c1000 and GMS77C1001 supports power saving modes to reduce power con- sumption. 1.2 features ? high-performance risc cpu: - 12-bit wide instructions and 8-bit wide data path - 33 single word instructions - 0.5k/1k words on-chip program memory - 25 bytes on-chip data memory - minimum instruction execution time 200ns @20mhz - operating speed: dc - 20 mhz clock input - seven special function hardware registers - two-level hardware stack ? peripheral features: - twelve programmable i/o lines - one 8-bit timer/counter with 8-bit programmable prescaler - power-on reset (por) - power fail detector : noise immunity circuit 2 level detect ( 3v, 2.5v ) - internal reset timer (irt) - watchdog timer (wdt) with on-chip rc oscilla- tor - programmable code-protection - power saving sleep mode - selectable oscillator options: configuration word rc: low-cost rc oscillator (200khz~4mhz) xt: standard crystal/resonator (455khz~4mhz) hf: high-speed crystal/resonator (4~20mhz) lf: power saving, low-frequency crystal/resonator (32~200khz) ? cmos technology: - low-power, high-speed cmos eprom technol- ogy - fully static design - wide-operating range: 2.5v to 5.5v @ rc, xt, lf 4.5v to 5.5v @ hf device name rom size ram size package gms77c1000 0.5k words(12-bit) 25 bytes 18 pdip, sop or 20 ssop GMS77C1001 1k words(12-bit) 25 bytes 18 pdip, sop or 20 ssop
gms77c1000/GMS77C1001 2 july. 2001 ver. 1.1 2. block diagram w stack 1 data memory 8-bit counter timer/ program memory pc wdt/ prescaler watch-dog timer instruction ra rb status system controller clock generator reset xin xout ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 v dd v ss power supply decoder rb5 rb6 rb7 ec0 wdt time out alu stack 2 option tmr0 power fail detector timing control configuration word trisa trisb
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 3 3. pin assignment v ss ra1 ra0 xin xout v dd rb7 rb6 rb5 ra2 ra3 ec0 reset /v pp v ss rb0 rb1 rb2 rb3 18 pdip or sop 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 rb4 ra1 ra0 xin xout v dd rb7 rb6 rb5 ra2 ra3 ec0 reset /v pp v ss rb0 rb1 rb2 rb3 20 ssop rb4 v dd 5 1 2 3 4 6 7 8 9 10 20 19 14 18 17 15 13 12 11 16
gms77c1000/GMS77C1001 4 july. 2001 ver. 1.1 4. package diagram 0.925 0.015 0.045 typ 0.10 typ 0.300 0.270 0 . 0 1 5 0 ~ 15 max 0.180 min 0.020 0.120 0.292 0.400 0.461 0.104 0.014 typ 0.050 0.005 0.0091 0 ~ 8 0.024 18 pdip 18 sop unit: inch max min 0.895 0.022 0.140 0.065 0 . 0 0 8 0.245 0.410 0.299 0.451 0.097 0.029 0.040 0.0125 0.0115
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 5 0.205 0.301 0.289 0.078 0.010 typ 0.0256 0.002 0.004 0 ~ 8 0.025 20 ssop unit: inch max min 0.311 0.212 0.278 0.068 0.015 0.037 0.008 0.008
gms77c1000/GMS77C1001 6 july. 2001 ver. 1.1 5. pin function v dd : supply voltage. v ss : circuit ground. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. ra0~ra3 : ra is an 4-bit, cmos, bidirectional i/o port. ra pins can be used as outputs or inputs according to 0 or 1 written the their port direction register(trisa). rb0~rb7 : rb is a 8-bit, cmos, bidirectional i/o port. rb pins can be used as outputs or inputs according to 0 or 1 written the their port direction register(trisb). ec0 : ec0 is an external clock input to timer0. it should be tied to v ss or v dd , if not in use, to reduce current con- sumption. legend : i =input, o = output, i/o = input/output, p = power, - = not used, ttl = ttl input, st = schmitt trigger input pin name dip, sop pin no. ssop pin no. in/out input levels function v dd 14 15,16 p- supply voltage v ss 55,6 p- circuit ground reset 44 ist reset signal input/programming voltage input. this pin is an active low reset to the device. voltage on the reset pin must not exceed v dd to avoid unintended entering of programming mode. x in 16 18 ist oscillator crystal input/external clock source input x out 15 17 o- oscillator crystal output. connects to crystal or resonator in crystal oscilla- tor mode. in rc mode, x out pin outputs clkout which has 1/4 the fre- quency of x in , and denotes the instruction cycle rate. ra0 17 19 i/o ttl 4-bit bi-directional i/o ports ra1 18 20 i/o ttl ra2 1 1 i/o ttl ra3 2 2 i/o ttl rb0 6 7 i/o ttl 8-bit bi-directional i/o ports rb1 7 8 i/o ttl rb2 8 9 i/o ttl rb3 9 10 i/o ttl rb4 10 11 i/o ttl rb5 11 12 i/o ttl rb6 12 13 i/o ttl rb7 13 14 i/o ttl ec0 3 3 ist clock input to timer0. must be tied to v dd or v ss , if not in use, to reduce current consumption. table 5-1 pinout description
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 7 6. port structures ? reset ? xin, xout v ss internal reset v ss xout xin amplifier varies with to internal clock v dd v ss xout xin v dd ? ? ? ? 4 ( xt, hf, lf mode ) en ( xt, hf, lf ) r f en ( rc ) ( rc mode ) the oscillation mode internal capacitance ( appx. 6pf ) to internal clock
gms77c1000/GMS77C1001 8 july. 2001 ver. 1.1 ? ra0~3/rb0~7 ?ec0 data bus data bus data bus data reg. direction reg. read v dd v ss v ss timer counter clock input v dd ec0
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 9 7. electrical characteristics 7.1 absolute maximum ratings supply voltage .............................................. -0 to +7.5 v storage temperature ................................-65 to +125 c voltage on reset with respect to v ss .......0.3 to 13.5v voltage on any pin with respect to v ss .-0.3 to v dd +0.3 maximum current out of v ss pin ........................150 ma maximum current into v dd pin ..........................100 ma maximum output current sunk by (i ol per i/o pin)25 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................20 ma maximum current ( s i ol ) .................................... 120 ma maximum current ( s i oh )...................................... 80 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 recommended operating conditions parameter symbol condition specifications unit min. max. supply voltage v dd f xin =20mhz 4.5 5.5 v f xin =4mhz 2.5 5.5 operating frequency f xin rc mode 0.2 4 mhz xt mode 0.455 4 hf mode 4 20 lf mode 32 200 khz operating temperature t opr -40 85 c
gms77c1000/GMS77C1001 10 july. 2001 ver. 1.1 7.3 dc characteristics (1) ? (t a =-40 c~+85 c) parameter symbol test condition specification unit min typ 1 1. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max supply voltage v dd v xt, rc, lf 2.5 5.5 hf 4.5 5.5 v dd start voltage to ensure power-on reset v por - v ss -v vdd rise rate s vdd 2 2. this parameter is characterized but not tested. 0.05 - - v/ms ram data retention voltage v dr -1.5- v power fail detection v pfd v normal level - 3 - low level - 2.5 - supply current i dd 3 3. the test conditions for all i dd measurements in nop execution are: x in = external square wave; all i/o pins tristated, pulled to v ss , ec0 = v dd , reset = v dd ; wdt disabled/enabled as specified. xt, rc 4 4. does not include current through r ext. the current through the resistor can be estimated by the formula; i r = v dd /2r ext (ma) x in = 4mhz, v dd = 5v -1.83.3ma hf x in = 20mhz, v dd = 5v -9.020ma lf x in = 32khz, v dd = 3v, wdt disabled -1740ua power down current i pd 5 5. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss as like measurement conditions of supply current. v dd = 3v, wdt enabled -1020 ua v dd = 3v, wdt disabled -0.255
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 11 7.4 dc electrical characteristics (2) ? (t a =-40 c~+85 c) parameter symbol test condition specification unit min typ 1 1. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage v ih v i/o ports (ttl) 0.25v dd +0.8 reset , ec0, (st) 0.85v dd v dd x in (st) rc only 0.85v dd x in (st) xt, hf, lf 0.7v dd input low voltage v il v i/o ports (ttl) 0.15v dd reset , ec0, (st) v ss 0.15v dd x in (st) rc only 0.15v dd x in (st) xt, hf, lf 0.3v dd hysteresis of schmitt trigger inputs v hys 0.15v dd 2 2. this parameter are characterized but not tested. v input leakage current i l v in = v dd or v ss ua x in (st) xt, hf, lf -3.0 0.5 3.0 other pins -1.0 0.2 1.0 output high voltage v oh v i/o ports i oh = -5.0ma, v dd = 4.5v v dd - 0.9 v dd x out i oh = -5.0ma, v dd = 4.5v, rc osc. output low voltage v ol v i/o ports i ol = 8.0ma, v dd = 4.5v v ss 0.8 x out i ol = 600ua, v dd = 4.5v, rc osc.
gms77c1000/GMS77C1001 12 july. 2001 ver. 1.1 7.5 ac electrical characteristics (1) ?(t a =-40 c~+85 c) parameter symbol test condition specification unit min typ max external clock input frequency f xin xt osc mode dc - 4.0 mhz hf osc mode dc - 20 mhz lf osc mode dc - 200 khz oscillator frequency 1 1. this parameter is characterized but not tested. f xin rc osc mode dc - 4.0 mhz xt osc mode 0.1 - 4.0 mhz hf osc mode 4.0 - 20 mhz lf osc mode 5.0 - 200 khz external clock input period t xin xt osc mode 250 - - ns hf osc mode 50 - - ns lf osc mode 5 - - us oscillator period 1 t xin rc osc mode 250 - 4.0 mhz xt osc mode 250 - 10,000 ns hf osc mode 50 - 250 ns lf osc mode 5 - 200 us clock in x in pin 1 low to high time t xin l t xin h xt osc mode 85 - - ns hf osc mode 20 - - ns lf osc mode 2 - - us clock in x in pin 1 rise or fall time t xin r t xin f xt osc mode - - 25 ns hf osc mode - - 25 ns lf osc mode - - 50 ns
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 13 7.6 ac electrical characteristics (2) ? (t a =-40 c~+85 c) parameter 1 1. these parameters are characterized but not tested. symbol test condition specification unit min typ 2 2. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max reset pulse width (low) t reset v dd = 5v 100 - - ns watchdog timer time-out period ( no-prescaler ) t wdt v dd = 5v 10 14 20 ms internal reset timer period t irt v dd = 5v 5710ms ec0 high or low pulse width t ec0 h t ec0 l t cy = 4 x t xin ns no prescaler 10 - - with prescaler 0.5t cy + 20 -- ec0 period t ec0 p n = prescaler value ( 1,2,4,......256 ) ns no prescaler 20 - - with prescaler (t cy +40) / n -- t xin r x in ec0 0.15v 0.85v dd 0.15v dd reset 0.15v dd 0.85v dd t ec0 h t xin t reset t xin f t xin h t xin l t ec0 h t ec0 p
gms77c1000/GMS77C1001 14 july. 2001 ver. 1.1 7.7 typical characteristics these graphs and tables are for design guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data is a statistical summary of data collected on units from different lots over a period of time. typical repre- sents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation ta= 25 c ta=25 c i dd - v dd 4 3 2 1 0 (ma) i dd 23 45 6 v dd (v) normal operation 16 12 8 4 0 (mhz) f xin 23 45 6 v dd (v) operating area 4mhz 24 f xin = 20mhz 20 32khz i ol - v ol , v dd =5v 32 24 16 8 0 (ma) i ol v ol (v) 0.4 0.8 1.2 1.6 2.0 40 i ol - v ol , v dd =3v 18 12 6 0 (ma) i ol v ol (v) 0.4 0.8 1.2 1.6 2.0 ta=25 c ta=25 c
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 15 i oh - v oh , v dd =5v -16 -12 -8 -4 0 (ma) i oh 0.5 1.0 1.5 v dd -v oh (v) -20 i oh - v oh , v dd =3v -6 -4 -2 0 (ma) i oh 0.5 1.0 1.5 -8 2.0 v dd -v oh (v) typical rc oscillator 4.5 3.0 1.5 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 7.5 6.0 3.5 4.5 5.5 ta=25 c r=3.3k r=5k r=10k r=100k typical rc oscillator 3.0 2.5 2.0 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 4.5 3.5 3.5 4.5 5.5 r=3.3k r=10k 0.5 1.0 1.5 r=5k typical rc oscillator 1.50 1.25 1.00 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 2.00 1.75 3.5 4.5 5.5 r=3.3k r=10k 0.25 0.50 0.75 r=5k cext=0pf ta=25 c cext=20pf ta=25 c cext=100pf 4.0 r=100k r=100k typical rc oscillator 0.6 0.5 0.4 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 0.8 0.7 3.5 4.5 5.5 r=3.3k r=10k 0.1 0.2 0.3 r=5k ta=25 c cext=300pf r=100k ta=25 c ta=25 c
gms77c1000/GMS77C1001 16 july. 2001 ver. 1.1 cext rext average fosc @ 5v,25 c 0pf 3.3k 7.48mhz 5k 6.36mhz 10k 4.04mhz 100k 529khz 20pf 3.3k 4.60mhz 5k 3.62mhz 10k 2.14mhz 100k 249khz 100pf 3.3k 1.75mhz 5k 1.31mhz 10k 734khz 100k 80khz 300pf 3.3k 702khz 5k 510khz 10k 283khz 100k 30khz table 7-1 rc oscillator frequencies
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 17 8. architecture 8.1 cpu architecture the gms700 core is a risc-based cpu and uses a modi- fied harvard architecture. this architecture uses two sepa- rate memories with separate address buses, one for the program memory and the other for the data memory. this architecture adapts 33 single word instructions that are 12- bit wide instruction and has an internal 2-stage pipeline (fetch and execute), which results in execution of one in- struction per single cycle(200ns @ 20mhz) except for pro- gram branches. the gms77c100x can address 1k x 12 bits program memory and 25 bytes data memory. and it can directly or indirectly address data memory. the gms700 core has three special function registers - pc, status and fsr - in data memory map and has atu (address translation unit) to provide address for data memory and has an 8-bit general purpose alu and work- ing register(w) as an accumulator. the w register consists of 8-bit register and it can not be an addressed register. figure 8-1 gms700 cpu block diagram instruction decode & control unit status fsr w alu instruction program memory address immediate data data bus data memory bus indirect address address translation unit pc with 2-level stack control signals alu status
gms77c1000/GMS77C1001 18 july. 2001 ver. 1.1 9. memory the gms77c1000/1001 has separate memory maps for program memory and data memory. program memory can only be read, not written to. it can be up to 1k words of program memory. data memory can be read and written to 32 bytes including special function registers. 9.1 program memory the program memory is organized as 0.5k, 12-bit wide words(gms77c1000) and 1k, 12-bit wide words(GMS77C1001). the program memory words are addressed sequentially by a program counter. increment- ing at location 1ff h (gms77c1000) or 3ff h (GMS77C1001) will cause a wrap around to 000 h . figure 9-1 and figure 9-2 show a map of program memo- ry. after reset, cpu begins execution from reset vector which is stored in address(1ff h : gms77c1000, 3ff h : GMS77C1001). 9.2 data memory the data memory consists of 25 bytes of ram and seven special function registers. the data memory locations are addressed directly or indirectly by using fsr. figure 9-3 shows a map of data memory. the special func- tion registers are mapped into the data memory.. figure 9-1 gms77c1000 program memory map and stack pc<8:0> stack level 1 stack level 2 reset vector on-chip program memory 000 h 0ff h 100 h 1ff h user memory space figure 9-2 GMS77C1001 program memory map and stack figure 9-3 gms77c1000/1 data memory map pc<9:0> stack level 1 stack level 2 reset vector on-chip program memory 000 h 0ff h 100 h 3ff h user memory space on-chip program memory 2ff h 300 h 1ff h 200 h (page 0) (page 1) 0f h 10 h 1f h indf tmr0 pcl status fsr ra rb 00 h 01 h 02 h 03 h 04 h 05 h 06 h file address special function registers 00 h 06 h 07 h data memory (sram) data memory (sram)
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 19 9.3 special function registers this devices has seven special function register that are the indf register, the program counter(pc), the status register, file select register(fsr), 8-bit timer(tmr0), and i/o data register(ra, rb). the special function registers are registers used by the cpu and peripheral functions to control the operation of the device (table 9-1). tmr0, ra and rb are not in the g700 cpu. they are lo- cated in each peripheral function blocks. all special func- tion register are placed on data memory map. the indf register is not a physical register and this register is used for indirect addressing mode... legend : shaded boxes = unimplemented or unused, - = unimplemented, read as 0 x = unknown, u = unchanged, q = see the tables in section 17 for possible values. 9.3.1 indf register the indf register is not physically implemented register, used for indirect addressing mode. if the indf register are accessed, cpu goes to indirect addressing mode. then cpu accesses the data memory which address is the con- tents of fsr. if the indf register are accessed in indirect addressing mode(i.e., fsr=00h), 00h will be loaded into data bus. this time, note the arithmetic status bits of status reg- ister may be affected. the fsr<4:0> bits are used to select data memory ad- dresses 00 h to 1f h . gms77c1000 and GMS77C1001 do not use banking. fsr<7:5> are unimplemented and read as '1's. name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power-on reset reset and wdt reset tris n/a i/o control registers (trisa, trisb) 1111 1111 1111 1111 option n/a contains control bits to configure timer0, timer0/wdt prescaler and pfd 0011 1111 0011 1111 indf 00 h uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu tmr0 01 h 8-bit real-time clock/counter xxxx xxxx uuuu uuuu pcl 02 h low order 8bits of pc 1111 1111 1111 1111 status 03 h - - pa0 to pd zdcc 0001 1xxx 000q quuu fsr 04 h indirect data memory address pointer 1xxx xxxx 1uuu uuuu ra 05 h - - - - ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu rb 06 h rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu table 9-1 special function register summary figure 9-4 direct/indirect addressing 40 40 (opcode) (fsr) location select location select data memory 00 h 0f h 10 h 1f h direct addressing indirect addressing
gms77c1000/GMS77C1001 20 july. 2001 ver. 1.1 9.3.2 tmr0 register the tmr0 register is a data register for 8-bit timer/ counter. in reset state, the tmr0 register is initialized with 00 h . 9.3.3 program counter (pc) the program counter contains the 10-bit address of the in- struction to be executed(9-bit address for gms77c1000). the lower 8 bits of the program counter are contained in the pcl register which can be provided by the instruction word for a call instruction, or any instruction where the pcl is the destination while the ninth bit of the program counter comes from the page address bit - pa0 of the sta- tus register(GMS77C1001 only). this is necessary to cause program branches across pro- gram memory page boundaries. prior to the execution of a branch operation, the user must initialize the pa0 bit of status register. the eighth bit of the program counter can come from the instruction word by execution of goto instruction, or can be cleared by execution of call or any instruction where the pcl is the destination. in reset state, the program counter is initialized with 1ff h (gms77c1000) or 3ff h (GMS77C1001). note: because pc<8> is cleared in the subroutine call in- struction, or any modify pcl instruction, all subrou- tine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). 9.3.4 stack operation the gms77c1000/1001 have a 2-level hardware stack. the stack register consists of two 9-bit save regis- ters(gms77c1000), 10-bit save registers(GMS77C1001). a physical transfer of register contents from the program counter to the stack or vice versa, and within the stack, oc- curs on call and return instructions. if more than two se- quential call instructions are executed, only the most recent two return address are stored. if more than two sequential return instructions are executed, the stack will be filled with the address previously stored in level 2. the stack cannot be read or written by program. jump instrunciton subroutine call instruction figure 9-5 loading of branch instruction - gms77c1000 pcl pc 80 instruction word pcl pc 87 0 instruction word reset to 0 jump instruction subroutine call instruction figure 9-6 loading of branch instruction - GMS77C1001 figure 9-7 operation of 2-level stack pcl pc 80 instruction word 9 pa0 pcl pc 87 0 instruction word 9 pa0 reset to 0 pc stack level1 stack level2 0 9(8) return return subroutine call GMS77C1001(gms77c1000) subroutine call
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 21 9.3.5 status register this register contains the arithmetic status of the alu, the reset status, and the page select bit for program memo- ries larger than 512 words. the status register can be the destination for any in- struction, as with any other register. if the status regis- ter is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. there- fore, the result of an instruction with the status register as destination may be different than intended. it is recommended that only instructions that do not affect status of cpu be used on status register. care should be exercised when writing to the status register as the alu status bits are updated upon completion of the write operation, possibly leaving the status register with a re- sult that is different than intended. in reset state, the sta- tus register is initialized with 00011xxx b . 9.3.6 fsr register the fsr register is an 8-bit register. the lower 5 bits are used to store indirect address for data memory. the upper 3 bits are unimplemented and read as 0. figure 9-9 shows how the fsr register can be used in indirect ad- dressing mode. in reset state, the fsr register is initialized with 1xxx_xxxx b . figure 9-8 status register - pa0 r/w to r pd r z r/w dc r/w c r/w bit7 bit0 pa0 : program memory page select bits 0 = page 0 (000h - 1ffh) - gms77c1000/1001 1 = page 1 (200h - 3ffh) - GMS77C1001 to : time-overflow bit 1 = after power-up, watchdog clear instruction, or entering power-down mode 0 = a watchdog timer time-overflow occurred pd : power-down bit 1 = after power-up or by the watchdog clear instruction 0 = by execution of power-down mode z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero dc : digit carry/borrow bit (for addition and subtraction) addition 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subtraction 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred c : carry/borrow bit (for additon,subtraction and rotation) addition 1 = a carry occurred 0 = a carry did not occur subtraction 1 = a borrow did not occur 0 = a borrow occurred rotation load bit with lsb or msb, respectively r = readable bit w = writable bit address ; 03 h reset value : 0001_1xxx -
gms77c1000/GMS77C1001 22 july. 2001 ver. 1.1 9.3.7 option register the option register consists of 8-bit write-only register and can not addressed. this register is able to control the status of pfd, tmr0/wdt prescaler and tmr0. to modify the option register, the content of w register are transferred to the option register by executing the option instruction. in reset state, the option register is initialized with 00111111 b . figure 9-9 fsr register and direct/indirect addressing mode fsr address : 04h 80 11 5 0 4 4 - -- 1 0 indirect addressing mode direct addressing mode data memory address instruction word opcode reset value: 1xxx_xxxx b figure 9-10 option register lowopt w pfden w t0cs w t0se w psa w ps2 w ps1 w ps0 w bit7 6 bit0 54321 lowopt : power-fail detection level select bit. 1 = lowered detection level (2.5v @ 5v) 0 = normal detection level (3v @ 5v) pfden : power-fail detection enable bit 1 = enable power-fail detection 0 = disable power-fail detection t0cs : timer 0 clock source select bit 1 = transition on ec0 pin 0 = internal instruction cycle clock t0se : timer 0 source edge select bit 1 = increment on high-to-low transition on ec0 0 = increment on low-to-high transition on ec0 psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to the timer 0 ps2-ps0 : prescaler rate select bits) bit value timer 0 rate wdt rate 000 1:2 1:2 (typ. 28ms) 001 1:4 1:4 (typ. 56ms) 010 1:8 1:8 (typ. 112ms) 011 1:16 1:16 (typ. 224ms) 100 1:32 1:32 (typ. 448ms) 101 1:64 1:64 (typ. 896ms) 110 1:128 1:128 (typ. 1792ms) 111 1:256 1:256 (typ. 3584ms) w = writable bit -n = value at por reset address ; 03 h reset value : 0011_1111
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 23 10. i/o ports the gms77c1000/1001 has a 4-bit i/o port(ra) and a 8- bit i/o port(rb). all pin have data(ra,rb) and direction(trisa,trisb) registers which can assign these ports as output or input. a 0 in the port direction registers configure the corre- sponding port pin as output. conversely, write 1 to the corresponding bit to specify it as input pin (hi-z state). for example, to use the even numbered bit of rb as output ports and the odd numbered bits as input ports, write 55 h to trisb register during initial setting as shown in figure 10-1. all the port direction registers in the gms77c1000/1001 have 1 written to them by reset function. this causes all port as input. 10.1 port ra ra is a 4-bit i/o register. each i/o pin can independently used as an input or an output through the port direction reg- ister, trisa. a 0 in the trisa register configure the corresponding port pin as output. conversely, write 1to the corresponding bit to specify it as input pin. bits 7-4 are unimplemented and read as '0's. 10.2 port rb rb is an 8-bit i/o register. each i/o pin can independently used as an input or an output through the port direction reg- ister, trisb. a 0 in the trisb register configure the corresponding port pin as output. conversely, write 1to the corresponding bit to specify it as input pin. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 10.3 i/o interfacing the equivalent circuit for an i/o port pin is shown in fig- ure 10-4. all ports may be used for both input and output operation. for input operations these ports are non-latching. any in- put must be present until read by an input instruction. the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corre- sponding direction control bit (in trisa, trisb) must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin can be programmed individu- ally as input or output.. 10.4 i/o successive operations the actual write to an i/o port happens at the end of an in- struction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 10-5). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the cpu, is executed. figure 10-1 example of port i/o assignment figure 10-2 ra port registers 0 port rb 7 1 6 0 5 1 4 0 3 1 2 0 1 1 0 out in out in out in out in write 55 h to port rb direction register trisb ra ra3 3 ra2 2 ra1 1 ra0 0 ra data register ra direction register trisa address : 05 h reset value : undefined address : n/a reset value : 0f h figure 10-3 rb port registers rb rb7 7 rb6 6 rb5 5 rb4 4 rb data register rb direction register trisb address : 06 h reset value : undefined address : n/a reset value : ff h rb3 3 rb2 2 rb1 1 rb0 0
gms77c1000/GMS77C1001 24 july. 2001 ver. 1.1 otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 10-4 equivalent circuit for a single i/o pin name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power-on reset reset and wdt reset tris n/a i/o control registers (trisa, trisb) 1111 1111 1111 1111 ra 05 h - - - - ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu rb 06 h rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu table 10-1 summary of port registers legend: shaded boxes = unimplemented or unused, - = unimplemented, read as 0, x = unknown, u = unchanged. data bus data bus data bus data reg. direction reg. read v dd v ss figure 10-5 successive i/o operation output rb pc rb7:rb0 instruction this example shows a write fetched q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc+1 pc+2 pc+3 read rb port no operation no operation port pin written here port pin read here to rb followed by a read from rb.
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 25 11. timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? 8-bit software programmable prescaler ? internal or external clock select ? edge select for external clock figure 11-1 is a simplified block diagram of the timer0 module, while figure 11-2 shows the electrical structure of the timer0 input . figure 11-1 block diagram of the timer0/wdt prescaler figure 11-2 electrical structure of ec0 pin t cy ( = f osc /4) 1 8-bit prescaler ec0 pin 0 sync with internal clocks tmr0 reg 8 data bus (2cycle delay) t0se 8 t0cs mux 0 1 mux 1 0 psa mux 8 - to - 1 mux watchdog timer mux ps2:ps0 psa psa 1 0 wdt time-out wdt enable bit clear eco p n pin r in schmitt trigger input buffer (1) note 1: esd protection circuits noise filter
gms77c1000/GMS77C1001 26 july. 2001 ver. 1.1 11.1 timer mode if the option register bit5(t0cs) is cleared, the timer mode is selected and is operated with internal system clock (t cy ). the timer0 module will increment every instruc- tion cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles. the user can work around this by writing an adjusted value to the tmr0 register. figure 11-3 and figure 11-4 show the timing diagram of timer. - no prescaler (psa=0) timer will increment every instruction cycle(q4). - with prescaler (psa=1) timer will increment with prescaler division ratio. @ ps2~ps0 = (1:2) ~ (1:256)counter mode 11.2 counter mode if the option register bit5(t0cs) is set, the counter mode is selected and operates with event clock input. in this mode, timer0 will increment either on every rising or falling edge of pin ec0. the incrementing edge is deter- mined by the source edge select bit t0se (option<4>). clearing the t0se bit selects the rising edge. figure 11-3 timer0 timing: internal clock/no prescale figure 11-4 timer0 timing: internal clock/prescaler 1:2 [ w tmr0 ] pc-1 tmr0 instruction fetch q1 q2 q3 q4 pc q1 q2 q3 q4 pc+1 q1 q2 q3 q4 pc+2 q1 q2 q3 q4 pc+3 q1 q2 q3 q4 pc+4 q1 q2 q3 q4 pc+5 q1 q2 q3 q4 pc+6 q1 q2 q3 q4 [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] t0 t0+1 t0+2 nt0 nt0+1 nt0+2 write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0+1 read tmr0 reads nt0+2 pc (program counter) instruction executed increment inhibited timer0 clock [ w tmr0 ] pc-1 tmr0 instruction fetch q1 q2 q3 q4 pc q1 q2 q3 q4 pc+1 q1 q2 q3 q4 pc+2 q1 q2 q3 q4 pc+3 q1 q2 q3 q4 pc+4 q1 q2 q3 q4 pc+5 q1 q2 q3 q4 pc+6 q1 q2 q3 q4 [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] [ tmr0 w ] t0 t0+1 nt0 nt0+1 pc (program counter) increment inhabited timer0 clock write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0+1 read tmr0 reads nt0+2 instruction executed
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 27 legend: x = unknown, u = unchanged. 11.3 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. al- so, there is a delay in the actual incrementing of timer0 af- ter synchronization. 11.3.1 external clock synchronization the synchronization of ec0 input with the internal phase clocks is accomplished by sampling ec0 clock or the pres- caler output on the q2 and q4 falling of the internal phase clocks. after the synchronization, counter increments on the next instruction cycle (q4). there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incrementing. figure 11-5 shows the syn- chronization and the increment of the counter mode. ? ec0 clock specification - no prescaler (psa = 0) high or low time(min) 3 2t xin + 20ns - with prescaler (psa = 1) high or low time(min) 3 4t xin + 40ns but, there is a noise filter on the ec0 pin, the minimum low or high time(10ns) should be required. 11.3.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actual- ly incrementing. figure 11-5 shows the delay from the ex- ternal clock edge to the timer incrementing. 11.4 prescaler the prescaler may be used by either the timer0 module or the watchdog timer, but not both. thus, a prescaler as- signment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is neither readable nor writable. the psa and ps2:ps0 bits (option<3:0>) determine prescaler assignment and prescale ratio. when the prescal- er is assigned to the timer0 module, prescale values of 1:2, name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power-on reset reset and wdt reset tmr0 01 h 8-bit real-time clock/counter xxxx xxxx uuuu uuuu option n/a lowopt pfden t0cs t0se psa ps2 ps1 ps0 0011 1111 0011 1111 table 11-1 registers associated with timer0 figure 11-5 timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 t0 t0+1 note 1: delay from clock input change to tmr0 increment is 3t xin to 7t xin . (duration of q = t xin ). q1 q2 q3 q4 t0+2 external clock input or prescaler output (2) external clock/prescaler output after sampling increment tmr0 (q4) tmr0 small pulse misses sampling (1) (3) therefore, the error in measuring the interval between two edges on tmr0 input = 4t xin max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs.
gms77c1000/GMS77C1001 28 july. 2001 ver. 1.1 1:4,..., 1:256 are selectable. when assigned to the timer0 module, all instructions writ- ing to the tmr0 register will clear the prescaler. when as- signed to wdt, a clrwdt instruction will clear the prescaler along with the wdt. on a reset, the prescaler contains all '0's.
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 29 12. configuration area the device configuration area can be programmed or left unprogrammed to select device configurations such as os- cillator type, security bit or watchdog timer enable bit. four memory locations [aaah ~ (aaa+3) h ] are desig- nated as customer id recording locations where the user can store check-sum or other customer identification num- bers. these area are not accessible during normal execu- tion but are readable and writable during program/verify mode. it is recommended that only the 4 least significant bits of id recording locations are used. figure 12-1 device configuration area bit0 3 - id0 bit11 4 - id1 - id2 - id3 aaa h aaa h +1 aaa h +2 aaa h +3 configuration word fff h figure 12-2 configuration word for gms77c1000/1001 bit11 bit0 4321 bit 3 cp : code protection bit. 1 = code protection disabled 0 = code protection enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hf oscillator 01 = xt oscillator 00 = lf oscillator address : fff h cp wdte fosc1 fosc0 - unimplemented, read as 0 configuration word
gms77c1000/GMS77C1001 30 july. 2001 ver. 1.1 13. oscillator circuits gms77c100x supports four user-selectable oscillator modes. the oscillator modes are selected by programming the appropriate values into the configuration word. - xt : crystal/resonator - hf : high speed crystal/resonator - lf : low speed and low power crystal - rc : external resistor/capacitor 13.1 xt, hf or lf mode in xt, lf or hf modes, a crystal or ceramic resonator is connected to the x in and x out pins to establish oscillation (figure 13-1). the gms77c100x oscillator design re- quires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufactur- ers specifications. bits 0 and 1 of the configuration register (fosc1:fosc2) are used to configure the different exter- nal resonator/crystal oscillator modes. these bits allow the selection of the appropriate gain setting for the internal driver to match the desired operating frequency. when in xt, lf or hf modes, the device can have an external clock source drive the x in pin (figure 13-2). in this case, the x out pin should be left open. note: these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for ap- propriate values of external components. note: these values are for design guidance only. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropri- ate values of external components. if you change from this device to another device, please verify oscillator characteristics in your application. 13.2 rc oscillation mode the external rc oscillator mode provides a cost-effective approach for applications that do not require a precise op- erating frequency. in this mode, the rc oscillator frequen- figure 13-1 crystal or ceramic resonator (hf, xt or lf osc configuration) figure 13-2 external clock input operation (hf, xt or lf osc configuration) x out x in to internal rf (2) sleep logic xtal c2 (1) c1 (1) note 1: see capacitor selection tables for recommended values of c1 and c2. 2: rf varies with the crystal chosen (approx. value = 9 m w). x out x in open gms77c100x clock from ext. system osc type resonator freq cap.range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 22-100 pf 15-68 pf 15-68 pf 22-100 pf 15-68 pf 15-68 pf hf 4.0 mhz 8.0 mhz 16.0 mhz 15-68 pf 10-68 pf 10-22 pf 15-68 pf 10-68 pf 10-22 pf table 13-1 capacitor selection for ceramic resonators osc type crystal freq cap.range c1 cap. range c2 lf 32 khz 1 100 khz 200 khz 1. for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. 15 pf 15-30 pf 15-30 pf 15 pf 30-47 pf 15-82 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-47 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15-30 pf 15-47 pf hf 4 mhz 8 mhz 20 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf table 13-2 capacitor selection for crystal
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 31 cy is a function of the supply voltage, the resistor(r) and capacitor(c) values, and the operating temperature. in addition, the oscillator frequency will vary from unit to unit due to normal manufacturing process variations. fur- thermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, espe- cially for low c values. the external r and c component tolerances contribute to oscillator frequency variation as well. the user also needs to take into account variation due to tolerance of external r and c components used. figure 13-3 shows how the r is connected to the gms77c100x. for rext values below 2.2 k w , the oscilla- tor operation may become unstable, or stop completely. for very high rext values (e.g., 1 m w ) the oscillator be- comes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . ta- ble 13-3 shows recommended value of rext and cext. although the oscillator will operate with no external ca- pacitor (cext = 0 pf), it is recommend using values above 20 pf for noise and stability reasons. with no or small ex- ternal capacitance, the oscillation frequency can vary dra- matically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the electrical specifications sections show r frequency variation from part to part due to normal process variation. also, see the electrical specifications sections for variation of os- cillator frequency due to v dd for given rext/cext values as well as frequency variation due to operating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the x out pin, and can be used for test purposes or to synchro- nize other logic. cext rext average f xin @ 5v, 25c 0pf 3.3k 5k 10k 100k 7.48mhz 6.36mhz 4.04mhz 529khz 20pf 3.3k 5k 10k 100k 4.60mhz 3.62mhz 2.14mhz 249khz 100pf 3.3k 5k 10k 100k 1.75mhz 1.31mhz 734khz 80khz 300pf 3.3k 5k 10k 100k 702khz 510khz 283khz 30khz table 13-3 rc oscillation frequencies figure 13-3 rc oscillation mode n r ext internal v dd x in x out clock f xin /4 c ext
gms77c1000/GMS77C1001 32 july. 2001 ver. 1.1 14. reset gms77c100x devices may be reset in one of the follow- ing ways: - power-on reset (por) - power-fail detect reset (pfdr) - reset (normal operation) - reset wake-up reset (from sleep) - wdt reset (normal operation) - wdt wake-up reset (from sleep) each one of these reset conditions causes the program counter to branch to reset vector address. (gms77c1000 is 1ff h and GMS77C1001 is 3ff h ). table 14-1 shows these reset conditions for the pcl and status registers. some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a reset state on power-on reset (por), pfdr, reset or wdt reset. a reset or wdt wake-up from sleep also results in a device reset, and not a continuation of operation before sleep. the to and pd bits (status <4:3>) are set or cleared depending on the different reset conditions. these bits may be used to determine the nature of the reset. table 14-2 lists a full description of reset states of all reg- isters. figure 14-1 shows a simplified block diagram of the on-chip reset circuit. condition pcl addr: 02 h status addr: 03 h power-on reset 1111 1111 0001 1xxx reset reset or pfd reset (normal operation) 1111 1111 000u uuuu 1 1. to and pd bits retain their last value until one of the other reset conditions occur. reset wake-up or pfd reset (from sleep) 1111 1111 0001 0uuu wdt reset (normal operation) 1111 1111 0000 uuuu 2 2. the clrwdt instruction will set the to and pd bits. legend : x = unknown, u = unchanged. wdt wake-up (from sleep) 1111 1111 0000 0uuu table 14-1 reset conditions for special registers register address power-on reset wake-up reset reset , pfdr, wdt reset wn/a xxxx xxxx uuuu uuuu uuuu uuuu tris n/a 1111 1111 1111 1111 1111 1111 option n/a 0011 1111 0011 1111 0011 1111 indf 00 h xxxx xxxx uuuu uuuu uuuu uuuu tmr0 01 h xxxx xxxx uuuu uuuu uuuu uuuu pcl 1 02 h 1111 1111 1111 1111 1111 1111 status 1 03 h 0001 1xxx 100q quuu 000q quuu fsr 04 h 1xxx xxxx 1uuu uuuu 1uuu uuuu porta 05 h ---- xxxx ---- uuuu ---- uuuu portb 06 h xxxx xxxx uuuu uuuu uuuu uuuu general purpose register files 07-1f h xxxx xxxx uuuu uuuu uuuu uuuu table 14-2 reset conditions for all registers 1. see table 14-1 for reset value for specific conditions. legend : - = unimplemented, read as 0, x = unknown, u = unchanged. q = see the tables in section 17 for possible values.
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 33 14.1 power-on reset (por) the gms77c100x family incorporates on-chip power- on reset (por) circuitry which provides an internal chip reset for most power-up situations. to use this feature, the user merely ties the reset /v pp pin to vdd. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 14-1. the power-on reset circuit and the internal reset timer circuit are closely related. on power-up, the reset latch is set and the irt is reset. the irt timer begins counting once it detects reset to be high. after the time-out peri- od, which is typically 7 ms (oscillation stabilization time), it will reset the reset latch and thus end the on-chip reset signal. figure 14-1 simplified block diagram of on-chip reset circuit v dd internal reset wdt time-overflow wdt power-on reset power-fail detect reset /v pp pin on-chip rc osc reset internal reset timer ( 8-bit asyn. ripple counter ) clear s r q q noise filter figure 14-2 time-out sequence on power-up (reset not tied to v dd ) v dd reset internal por irt timer-out internal reset t irt
gms77c1000/GMS77C1001 34 july. 2001 ver. 1.1 a power-up example where reset is not tied to vdd is shown in figure 14-2. vdd is allowed to rise and stabilize before bringing reset high. the chip will actually come out of reset tirt after reset goes high and por, pfdr is released. in figure 14-3, the on-chip power-on reset feature is be- ing used (reset and vdd are tied together). the vdd is stable before the internal reset timer times out and there is no problem in getting a proper reset. however, figure 14- 4 depicts a problem situation where vdd rises too slowly. the time between when the irt senses a high on the re- set /v pp pin, and when the reset /v pp pin (and vdd) actually reach their full value, is too long. in this situation, when the internal reset timer times out, vdd has not reached the vdd (min) value and the chip is, therefore, not guaranteed to function correctly. for such situations, we recommend that external r circuits be used to achieve longer por delay times (figure 14-5). note: when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. figure 14-3 time-out sequence on power-up (reset tioed to v dd ): fast v dd rise time figure 14-4 time-out sequence on power-up (reset tioed to v dd ): slow v dd rise time v dd reset internal por irt timer-out internal reset t irt v dd reset internal por irt timer-out internal reset t irt - when v dd rise slowly, the t irt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, v1 3 v dd min.
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 35 the por circuit does not produce an internal reset when v dd declines. 14.2 internal reset timer (irt) the internal reset timer (irt) provides a fixed 7 ms nom- inal time-out on reset. the irt operates on an internal rc oscillator. the processor is kept in reset as long as the irt is active. the irt delay allows vdd to rise above vdd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. the on-chip irt keeps the device in a reset condition for approximately 7 ms after the voltage on the reset /v pp pin has reached a logic high (v ih ) level and por released. thus, external rc networks connected to the reset input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted appli- cations. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. the irt will also be triggered upon a watchdog timer time-out. this is particularly important for applications us- ing the wdt to wake the gms77c100x from sleep mode automatically. figure 14-5 external power-on reset circuit (for slow vdd power- up) reset - external power-on reset circuit is required only if vdd power-up is too slow. the diode d helps discharge the capacitor quickly when vdd powers down. - r < 40 k w is recommended to make sure that voltage drop across r does not violate the device electrical specifi- cation . - r1 = 100w to 1 kw will limit any current flowing into reset from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). r r1 d c v dd v dd
gms77c1000/GMS77C1001 36 july. 2001 ver. 1.1 15. watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the x in pin. that means that the wdt will run even if the clock on the x in and x out pins have been stopped, for ex- ample, by execution of a sleep instruction. during nor- mal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watch- dog timer reset. the wdt can be permanently disabled by programming the configuration bit wdte as a '0' (figure 12-2). refer to the gms77c100x programming specifications to deter- mine how to access the configuration word. 15.1 wdt period the wdt has a nominal time-out period of 14 ms, (with no prescaler). if a longer time-out period is desired, a pres- caler with a division ratio of up to 1:256 can be assigned to the wdt (under software control) by writing to the op- tion register. thus, time-out a period of a nominal 3.5 seconds can be realized. these periods vary with tempera- ture, v dd and part-to-part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 15.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. figure 15-1 watchdog timer block diagram name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power-on reset reset and wdt reset option n/a lowopt pfden t0cs t0se psa ps2 ps1 ps0 0011 1111 0011 1111 table 15-1 summary of registers associated with the watchdog timer postscaler 8 1 0 psa mux 8 - to - 1 mux 8-bit asynchronous ripple counter mux ps2:ps0 psa 1 0 wdt time-out to tmr0 from tmr0 clock source clear on-chip rc-osc watchdog timer enable wdte sleep clearing wdt sleep clearing wdt psa
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 37 16. power-down mode (sleep) for applications where power consumption is a critical factor, device provides power down mode with watchdog operation. executing of sleep instruction is entrance to sleep mode. in the sleep mode, oscillator is turn off and system clock is disable and all functions is stop, but all registers and ram data is held. the wake-up sources from sleep mode are external reset pin reset and watchdog time-overflow reset. 16.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had be- fore the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time- out does not drive the reset pin low. for lowest current consumption while powered down, the ec0 input should be at v dd or v ss and the reset pin must be at a logic high level . figure 16-1 timing diagram of wake-up from sleep mode due to external reset pin reset figure 16-2 timing diagram of wake-up from sleep mode due to watchdog time-overflow reset ~ ~ oscillator (x in pin) ~ ~ ~ ~ ~ ~ ~ ~ internal system clock ~ ~ internal ~ ~ ~ ~ ~ ~ reset reset fetch sleep execute sleep fetch reset vector ~ ~ ~ ~ instruction t irt ~ ~ oscillator (x in pin) ~ ~ ~ ~ ~ ~ ~ ~ internal system clock ~ ~ internal ~ ~ ~ ~ ~ ~ reset wdt fetch sleep execute sleep fetch reset vector ~ ~ ~ ~ instruction t irt overflow
gms77c1000/GMS77C1001 38 july. 2001 ver. 1.1 16.2 wake-up from sleep the device can wake up from sleep through one of the following events: 1. an external reset input on reset pin. 2. a watchdog timer time-out reset (if wdt was en- abled). 3. pfd reset both of these events cause a device reset. the to and pd bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the wdt is cleared when the device wakes from sleep, re- gardless of the wake-up source. 16.3 minimizing current consumption the sleep mode is designed to reduce power consump- tion. to minimize current drawn during sleep mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. it should be set properly that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if uncertain voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. note: in the sleep operation, the power dissipation asso- ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat- ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the sleep feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. figure 16-3 application example of unused input port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configure as an input, input level should be closed to 0v or 5v to avoid power consumption.
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 39 figure 16-4 application example of unused output port output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port.
gms77c1000/GMS77C1001 40 july. 2001 ver. 1.1 17. time-out sequence and power down status bits (to /pd ) the to and pd bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a reset or watchdog timer (wdt) reset, or a reset or wdt wake-up reset. these status bits are only affected by events listed in table 17-2. note: a wdt time-out will occur regardless of the status of the to bit. a sleep instruction will be executed, regardless of the status of the pd bit. table 14-1 lists the reset conditions for the special function registers, while table 14-2 lists the reset conditions for all the registers. to pd reset was caused by 1 1 power-up(por) uu reset or pfd reset (normal operation) 1 1. the to and pd bits maintain their status ( u ) until a reset occurs. a low-pulse on the reset input does not change the to and pd status bits. 10 reset wake-up or pfd reset (from sleep) 0 1 wdt reset (normal operation) 0 0 wdt wake-up reset (from sleep) table 17-1 to /pd status after reset event to pd remarks power-up 1 1 wdt time-out 0 u no effect on pd sleep instruction 1 0 clrwdt instruction 1 1 table 17-2 events affecting to /pd status bits
gms77c1000/GMS77C1001 july. 2001 ver. 1.1 41 18. power fail detection processor gms77c1000x has an on-chip power fail detection cir- cuitry to immunize against power noise. if v dd falls below a level for longer 100ns, the power fail detection processor may reset mcu and preserve the de- vice from the malfunction due to power noise. the bit6(pfden) of option register activates the pfd circuit, and bit7(lowopt) lowers the detection level of the power noise. the normal detection level is typically 3v and the lowered detection level is typically 2.5v. fig- ure 18-2 shows a power fail detection situations where the detection level is selected by lowopt bit. note: the pfd circuit is not implemented on the in circuit emulator, user can not experiment with it. there fore, after final development user program, this function may be experimented on otp figure 18-1 power fail detection processor lowopt pfden t0cs t0se psa ps2 ps1 ps0 bit7 6 bit0 54321 bit 7 lowopt : power-fail detection level select bit. 1 = lowered detection level (typ. 2.5v @ 5v) 0 = normal detection level (typ. 3v @ 5v) bit 6 pfden : power-fail detection enable bit 1 = enable power-fail detection 0 = disable power-fail detection option register figure 18-2 power fail detection situations internal reset v dd v dd =3v v dr t nvdd 3 100ns pfden = 1 pfdr t irt internal reset v dd v dd =2.5v v dr t nvdd 3 100ns pfdr t irt internal reset v dd v dd =3/(2.5)v v dr pfdr t irt por lowopt = 0 pfden = 1 lowopt = 0/1 v dd v dr pfden = 1 lowopt = 1 when vdd falls below approximately 1v level, power-on reset may occur.

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